VC4ASM - Instruction extensions

↑ Top, ALU, mov, ldi, nop, read, Semaphore, Branch, Signal, Conditional assignment, Pack/unpack

Set flags

opcode.setf ...
opcode.sf ...
opcode destination.setf, ...
opcode destination.sf, ...

This flag causes an instruction to set the flags according to the destination value. See opcode table.

Conditional assignment

All ALU instructions and load immediate can use conditional assignment for the destination operand. The condition code can be applied to the opcode as well as to the destination operand.

opcode.ifcc destination, ...
opcode destination.cc, ...

cc

Condition code.

`cc`	Flag	Value	Description
`nz, zc`	Z	0	non zero
`z, zs`	Z	1	zero
`nn, nc`	N	0	non negative
`n, ns`	N	1	negative
`cc`	C	0	carry clear
`c, cs`	C	1	carry set

Example

mov.ifnz r0, ra7
mov r0.z, rb7

Pack and unpack

All ALU instructions including mov and ldi can be extended by pack operations.

opcode.packxx destination, ...
opcode destination.xx, ...
opcode.unpackxx ...
opcode ... source.xx

xx: Pack or unpack mode.

Pack/unpack modes

Format: B[O][s][i|f]
B: number of bits in the packed format
O: offset in the packed data if packed data is less than 32 bit. a = least significant packed word, b = ...)
s: use saturation. This is ignored on unpack modes when assigned to a symbol.
i: use integer pack mode
f: use floating point pack mode, i.e. unpack type is float.

`xx`	unpacked type	packed type	byte mask	pack		unpack
`xx`	unpacked type	packed type	byte mask	conversion	restrict destination	conversion	restrict source
`32`	any	any	`3 2 1 0`	`x`		`x`
`32s 32si`	`int32`	`int32`	`3 2 1 0`	`min(0x7fffffff, max(-0x80000000, x))` for `add` instruction, `min(0x80000000, max(-0x80000001, x))` for `sub` instruction, other instructions seem not to support this pack mode.	reg A & `add`/`sub` only	n/a
`16a`	`16ai` or `16af` depending on the context ⁽¹⁾
`16ai`	`int16`	`int16`	`_ _ 1 0`	`x & 0xffff`	reg A & no float	`x`	reg A & no float
`16af`	`float32`	`float16`	`_ _ 1 0`	`x`	reg A & float only	`x`	reg A & float \| r4
`16as 16asi`	`int32`	`int16`	`_ _ 1 0`	`min(0x7fff, max(-0x8000, x))`	reg A & no float	same as `16a`(`i`)
`16b`	`16ai` or `16af` depending on the context ⁽¹⁾
`16bi`	`int16`	`int16`	`1 0 _ _`	`x & 0xffff`	reg A & no float	`x`	reg A & no float
`16bf`	`float32`	`float16`	`1 0 _ _`	`x`	reg A & float only	`x`	reg A & float \| r4
`16bs 16bsi`	`int32`	`int16`	`1 0 _ _`	`min(0x7fff, max(-0x8000, x))`	reg A & no float	same as `16b`(`i`)
`8888 8abcd 8888i 8abcdi`	`uint8`	`uint32`	`0 0 0 0`	`(x & 0xff) * 0x01010101`	reg A	n/a
`8888s 8abcds`	`8888si` or `8888sf` depending on the context ⁽¹⁾					n/a
`8888si 8abcdsi`	`uint8`	`uint32`	`0 0 0 0`	`min(255, max(0, x))` `* 0x01010101`	reg A	n/a
`8888sf 8abcdsf`	`float32`	`uint32`	`0 0 0 0`	`min(255, max(0, x255))` ` 0x01010101`	MUL ALU	n/a
`8a`		`uint8`	`_ _ _ 0`	same as `8ai`		`8ai` or `8af` depending on the context ⁽¹⁾
`8ai`	`uint8`	`uint8`	`_ _ _ 0`	`x & 0xff`	reg A	`x`	reg A & no float
`8af`	`float32`	`uint8`	`_ _ _ 0`	n/a		`x / 255`	reg A & float \| r4
`8as`		`uint8`	`_ _ _ 0`	`8asi` or `8asf` depending on the context ⁽¹⁾		same as `8a`
`8asi`	`int32`	`uint8`	`_ _ _ 0`	`min(255, max(0, x))`	reg A	same as `8ai`
`8asf`	`float32`	`uint8`	`_ _ _ 0`	`min(255, max(0, x*255))`	MUL ALU	same as `8af`
`8b`		`uint8`	`_ _ 0 _`	same as `8ai`		`8ai` or `8af` depending on the context ⁽¹⁾
`8bi`	`uint8`	`uint8`	`_ _ 0 _`	`x & 0xff`	reg A	`x`	reg A & no float
`8bf`	`float32`	`uint8`	`_ _ 0 _`	n/a		`x / 255`	reg A & float \| r4
`8bs`		`uint8`	`_ _ 0 _`	`8asi` or `8asf` depending on the context ⁽¹⁾		same as `8a`
`8bsi`	`int32`	`uint8`	`_ _ 0 _`	`min(255, max(0, x))`	reg A	same as `8ai`
`8bsf`	`float32`	`uint8`	`_ _ 0 _`	`min(255, max(0, x*255))`	MUL ALU	same as `8af`
`8c`		`uint8`	`_ 0 _ _`	same as `8ai`		`8ai` or `8af` depending on the context ⁽¹⁾
`8ci`	`uint8`	`uint8`	`_ 0 _ _`	`x & 0xff`	reg A	`x`	reg A & no float
`8cf`	`float32`	`uint8`	`_ 0 _ _`	n/a		`x / 255`	reg A & float \| r4
`8cs`		`uint8`	`_ 0 _ _`	`8asi` or `8asf` depending on the context ⁽¹⁾		same as `8a`
`8csi`	`int32`	`uint8`	`_ 0 _ _`	`min(255, max(0, x))`	reg A	same as `8ai`
`8csf`	`float32`	`uint8`	`_ 0 _ _`	`min(255, max(0, x*255))`	MUL ALU	same as `8af`
`8d`		`uint8`	`0 _ _ _`	same as `8ai`		`8ai` or `8af` depending on the context ⁽¹⁾
`8di`	`uint8`	`uint8`	`0 _ _ _`	`x & 0xff`	reg A	`x`	reg A & no float
`8df`	`float32`	`uint8`	`0 _ _ _`	n/a		`x / 255`	reg A & float \| r4
`8ds`		`uint8`	`0 _ _ _`	`8asi` or `8asf` depending on the context ⁽¹⁾		same as `8a`
`8dsi`	`int32`	`uint8`	`0 _ _ _`	`min(255, max(0, x))`	reg A	same as `8ai`
`8dsf`	`float32`	`uint8`	`0 _ _ _`	`min(255, max(0, x*255))`	MUL ALU	same as `8af`
`8dr`	`uint32`	`uint8`	`0 _ _ _`	n/a		`x * 0x01010101`	reg A \| r4

Note (1) It is strongly recommended to use the pack/unpack modes that specify whether an integer or floating point operation should be used. vc4asm tries to guess this otherwise but you should avoid surprises.